Section: New Results

European Initiatives

NOE High Performance Embedded Architectures and Compilation (HiPEAC)

Participant : Olivier Zendra.

The TRIO team is involved in the HiPEAC (High Performance Embedded Architecture and Compilation) European Network of Excellence (NoE). Olivier Zendra was initiator and leader in this context of a cluster of European Researchers “Architecture-aware compiler solutions for energy issues in embedded systems” from mid-2007 to mid-2009. A STREP proposal tentatively titled "Integrated and generic energy-aware adaptation for extreme computing systems" is currently being written, mostly in the context of this network of excellence, for submission in Call ICT 2011.9.8 FET Proactive: Minimising Energy Consumption of Computing to the Limit (MINECC).

PROARTIS - Probabilistically Analysable Real-Time Systems

Participants : Liliana Cucu-Grosjean, Luca Santinelli, Codé Lo, Dorin Maxim.

PROARTIS (http://www.proartis-project.eu/ ) is a STREP project within the FP7 call and it started on February 2010. It has six partners: Barcelona Supercomputing, University of York, University of Padova, INRIA and Airbus. The overarching objective of the PROARTIS project is to facilitate a probabilistic approach to timing analysis. The proposed approach will concentrate on proving that pathological timing cases can only arise with negligible probability, instead of struggling to eradicate them, which is arguably not possible and could severely degrade performance. This will be a major turn from previous approaches that seek analyzability by trying to predict with cycle accuracy the state of hardware and software through analysis.

The PROARTIS project will facilitate the production of analysable CRTE systems on advanced hardware platforms with features such as memory hierarchies and multi core processors. PROARTIS has the following overall strategic industrial goals:

• Increased performance, reliability and reduced costs by enabling critical real-time systems to take full advantage of advanced hardware like deep memory hierarchies and multi core processors. The use of these features will allow designers to schedule more tasks while reducing the weight, power consumption and the size of the whole system and maintaining the desired predictability. It will also reduce the risk of temporal budget overruns. Application-level tasks will have an execution behaviour free (with sufficient low probability) from pathological temporal overruns.

• Increased productivity by enabling software engineers to develop more complex real-time software systems through timing-aware systems that reveal crucial timing details while dramatically simplifying analysis. For example, memory latencies will be predicted with less effort, requiring knowledge only of the total number of memory accesses, rather than the exact memory addresses and memory access patterns.

• Reduced time-to-market by enabling trustworthy WCET and other analyses for large-scale real-time systems that will dramatically reduce testing time.

The work within this project during 2011 lead to the following two publications: [11] and [35] .

TIMMO-2-USE - Timing Model - TOols, algorithms, languages, methodology, USE cases

Participants : Nicolas Navet, Françoise Simonot-Lion, Liliana Cucu-Grosjean, Ammar Oulamara, Luca Santinelli.

TIMMO-2-USE (http://timmo-2-use.org/ is an ITEA 2 European project and it started in November 2010.

TIMMO-2-USE will address the specification, transition and exchange of different types of timing information throughout different steps of the development process. The general goal is to evaluate and enhance standards for different applications in the development by different technical use cases covering multiple abstraction levels and tools. For this, TIMMO-2-USE will bring the AUTOSAR standard, TADL and EAST-ADL2 into different applications like WCET analysis and in-the-loop scenarios. This will bring new algorithms and tools for the transition and conversion of timing information between different tools and abstraction level based on a new advanced methodology which, in turn, will be based on a combination of the TIMMO and the ATESST2 methodologies. The main impact of TIMMO-2-USE will be:

• Improved, predictable development cycle: An extended and further developed infrastructure for handling timing constraints, containing additional features, will increase the predictability and effectiveness of the development cycle even more. As a result, both development cost and development time are expected to go down due to fewer costly design iterations, while at the same time the resulting design will moreover be more reliable.

• Reduced time-to-market by massive reuse: Reusing components annotated with timing information for the construction of a new system will enable the derivation of more accurate system timing behaviour at early development stages. Therefore the system can be developed with a reduced number of design iterations.

• More efficient communication and collaboration between different parties involved in development: This will support cooperative development scenarios and reduce the risk of mutual misunderstanding between different parties contributing to the design of the same system, for example OEMs and Tier-1 suppliers, and lead to safer and more accurate systems.

• Reduced development risk: A formal and unambiguous foundation for reasoning about time provides a steady basis and a common ground for better cooperation between tools with respect to timing information based on commonly agreed, industry-wide standards like AUTOSAR. The project will further develop methodologies and languages developed in ATESST2 and TIMMO. TADL (Timing Augmented Description Language) and EAST-ADL2 were introduced as a major leap forward and will be further adapted and extended in TIMMO-2-USE.